TUIEN=0, CKDV=0000, CKS=0, DWL=others, MST=0, BCKP=0, LRCKP=0, PDTA=0, ROIEN=0, DEL=0, RUIEN=0, MUEN=0, IIEN=0, TOIEN=0, SPDP=0, TEN=0, REN=0, SWL=000, SDTA=0
Control Register
| REN | Receive Enable 0 (0): Disables the receive operation. 1 (1): Enables the receive operation. |
| TEN | Transmit Enable 0 (0): Disables the transmit operation. 1 (1): Enables the transmit operation. |
| Reserved | This bit is read as 0. The write value should be 0. |
| MUEN | Mute Enable 0 (0): Disables muting on the next frame boundary 1 (1): Enables muting on the next frame boundary. |
| CKDV | Selects Bit Clock Division Ratio 0 (others): Setting prohibited 0 (0000): AUDIO_MCK 1 (0001): AUDIO_MCK/2 2 (0010): AUDIO_MCK/4 3 (0011): AUDIO_MCK/8 4 (0100): AUDIO_MCK/16 5 (0101): AUDIO_MCK/32 6 (0110): AUDIO_MCK/64 7 (0111): AUDIO_MCK/128 8 (1000): AUDIO_MCK/6 9 (1001): AUDIO_MCK/12 10 (1010): AUDIO_MCK/24 11 (1011): AUDIO_MCK/48 12 (1100): AUDIO_MCK/96 |
| DEL | Selects Serial Data Delay 0 (0): Delay of one cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0 1 (1): No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0 In the monaural format, this bit controls the waveform of SSILRCK/SSIFS. |
| PDTA | Selects Placement Data Alignment 0 (0): Left-justifies placement data (SSIFTDR, SSIFRDR) 1 (1): Right-justifies placement data (SSIFTDR, SSIFRDR). |
| SDTA | Selects Serial Data Alignment 0 (0): Transmits and receives serial data first and then padding bits 1 (1): Transmit and receives padding bits first and then serial data. |
| SPDP | Selects Serial Padding Polarity 0 (0): Padding data is at a low level 1 (1): Padding data is at a high level. |
| LRCKP | Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal 0 (0): The initial value is at a high level The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS 1 (1): The initial value is at a low level The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS. |
| BCKP | Selects Bit Clock Polarity 0 (0): SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a rising edge of SSIBCK) 1 (1): SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a falling edge of SSIBCK). |
| MST | Master Enable 0 (0): Slave-mode communication 1 (1): Master-mode communication. |
| Reserved | This bit is read as 0. The write value should be 0. |
| SWL | Selects System Word Length 0 (000): 8 bits 1 (001): 16 bits 2 (010): 24 bits 3 (011): 32 bits 4 (100): 48 bits 5 (101): 64 bits 6 (110): 128 bits 7 (111): 256 bits. |
| DWL | Selects Data Word Length 0 (000): 8 bits 0 (others): Settings other than above are prohibited. 1 (001): 16 bits 2 (010): 18 bits 3 (011): 20 bits 4 (100): 22 bits 5 (101): 24 bits 6 (110): 32 bits |
| Reserved | These bits are read as 000. The write value should be 000. |
| IIEN | Idle Mode Interrupt Output Enable 0 (0): Disables idle mode interrupt output 1 (1): Enables idle mode interrupt output. |
| ROIEN | Receive Overflow Interrupt Output Enable 0 (0): Disables receive overflow interrupt output 1 (1): Enables receive overflow interrupt output. |
| RUIEN | Receive Underflow Interrupt Output Enable 0 (0): Disables receive underflow interrupt output 1 (1): Enables receive underflow interrupt output. |
| TOIEN | Transmit Overflow Interrupt Output Enable 0 (0): Disables transmit overflow interrupt output 1 (1): Enables transmit overflow interrupt output. |
| TUIEN | Transmit Underflow Interrupt Output Enable 0 (0): Disables transmit underflow interrupt output 1 (1): Enables transmit underflow interrupt output. |
| CKS | Selects an Audio Clock for Master-mode Communication 0 (0): Selects the AUDIO_CLK input 1 (1): Selects the GTIOC1A (GPT output). |
| Reserved | This bit is read as 0. The write value should be 0. |